Echo canceling method and device for multiplex line

ABSTRACT

The present invention relates to an echo canceling method and apparatus for simultaneously erasing echoes produced on a plurality of transmission paths.  
     It is an object of the present invention to provide an echo canceling method and apparatus for multiplexed lines which require a short convergence time and a less amount of operations.  
     As a means for solving the problem of the present invention, the echo canceling apparatus has a control circuit ( 70 ) which receives information on convergence degrees and input signal intensities from a plurality of adaptive filters ( 80, 81, 82 ) to distribute a number of coefficient updates to each adaptive filter corresponding to the information.

TECHNICAL FIELD

[0001] The present invention relates to an echo canceling method andapparatus for simultaneously canceling echoes produced on a plurality oftransmission lines.

BACKGROUND ART

[0002] Regarding the techniques of canceling echoes leaking from thetransmitter side to the receiver side on the 4-line side of a 2-4 wirehybrid transformer circuit, there is known an echo canceler described in“Adaptive Signal Processing”, 1985, Prentice-Hall Inc., USA (reference1).

[0003] The echo canceler employs an adaptive filter having a number oftap coefficients equal to or larger than an impulse response length ofan echo path to produce a pseudo echo (echo replica) corresponding to atransmission signal, thereby operating to suppress an echo leaking froma transmission circuit to a reception circuit on the four-line side ofthe 2-4 wire hybrid transformer circuit.

[0004] In this event, each tap coefficient of the adaptive filter ismodified by correlating the transmission signal to an error signal whichis calculated by subtracting the echo replica from a mixed signalcomprising a mixture of the echo and a received signal.

[0005] As a typical coefficient adaptation algorithm for such anadaptive filter, there are known an LMS algorithm described in theaforementioned Reference 1, and a normalizing LMS (NLMS) algorithmdescribed in “Adaptive Filters,” 1985, Kulwer Academic Publishers, USA(Reference 2).

[0006] On an actual communication line, a plurality of subscriber linesare multiplexed to form multiplexed lines for further improvingefficiency of the transmission capacity. In such a case, echo cancelersfor canceling echoes in a 2-4 wire hybrid transformer circuit areequipped in a multiplexer as many as the number of multiplexed lines. Adesign for permitting a reduction in the total amount of operations insuch an echo canceler for multiplexed lines is described in Proceedingsof Symposium on Digital Signal Processing of the Institute ofElectronics, Information and Communication Engineers of Japan, pp.671-676, November 1999 (Reference 3). FIG. 1 illustrates theconfiguration of multiplexed echo cancelers described in Reference 3when the number of multiplexes is three.

[0007] On a first line, a transmission signal fed to transmission signalinput terminal 1 is sent to a transmission path from transmission signaloutput terminal 2, and sent to a 2-line side in 2-4 wire hybridtransformer circuit 3, wherein a portion of the transmission signalleaks into a reception side as an echo due to mismatch in impedance andthe like.

[0008] This echo is fed from received signal input terminal 4, and issupplied to subtractor 5. On the other hand, adaptive filter 86 receivesinput signal 700 supplied to transmission signal input terminal 1, andproduces echo replica 701 through a convolution with a coefficient valueof adaptive filter 86 modified on the basis of error signal 702, whichis an output of subtractor 5. Subtractor 5 subtracts echo replica 701delivered from adaptive filter 86 from the echo leaking into thereception side, and transfers the result of the subtraction thuscalculated to received signal output terminal 6. The result of thesubtraction is also fed back simultaneously to adaptive filter 86 aserror signal 702 for updating the coefficients.

[0009] Control circuit 79 receives step sizes 601, 603, 605 fromadaptive filters 86, 87, 88, respectively, and evaluates them. Since thestep sizes increase from initial values and decreases as thecoefficients are updated, they represent to what extent adaptive filters86, 87, 88 converge. Control circuit 79 supplies coefficient updatecontrol signals 602, 604, 606 at predefined time intervals correspondingto adaptive filters 86, 87, 88. Coefficient update control signals 602,604, 606 are information which determines how many times the respectiveadaptive filters update coefficients in the predetermined time interval,and are determined depending on the result of the evaluation on the stepsizes. Since the configuration and operation of the echo cancelers in asecond and a third line in FIG. 1 are completely the same as those ofthe first line, description thereon is omitted.

[0010] Since the conventional echo canceler for multiplexed lines doesnot need the number of operations which increases in proportion to thenumber of multiplexed lines, the amount of operations can be reduced.

[0011] However, when an input signal is an audio signal, an allocatednumber of times the coefficients are updated may not be used but wastedin some cases. This is because the coefficients are not updated when aninput signal has a small amplitude, so that even if coefficient updatesare allocated to an adaptive filter associated with such a line, theadaptive filter does not substantially update the coefficients. In otherwords, the number of operations associated with the allocatedcoefficient updates may include waste.

DISCLOSURE OF THE INVENTION

[0012] In view of the foregoing problem, it is an object of the presentinvention to provide an echo canceling method and apparatus formultiplexed lines which only require a small number of operations.

[0013] The echo canceling method and apparatus for multiplexed linesaccording to the present invention evaluate convergence degrees ofadaptive filters and input signal intensities on a plurality of lines,and allocate predefined numbers of coefficient updates to the respectivelines in accordance with the convergence degrees and the signalintensities on the respective lines.

[0014] More specifically, a control circuit is provided for receivinginformation on the convergence degree and information on an input signalfrom an adaptive filter connected to each line to allocate a number ofcoefficient updates corresponding thereto to each adaptive filter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a block diagram illustrating the configuration of aprior art example;

[0016]FIG. 2 is a block diagram illustrating a first embodiment of thepresent invention;

[0017]FIG. 3 is an example of the procedure for determining acoefficient update order schedule;

[0018]FIG. 4 is a block diagram illustrating the configuration of anadaptive filter according to the first embodiment of the presentinvention;

[0019]FIG. 5 is a block diagram illustrating the configuration of acoefficient generator circuit in the adaptive filter according to thefirst embodiment of the present invention;

[0020]FIG. 6 is a block diagram illustrating an adaptive filteraccording to a second embodiment of the present invention;

[0021]FIG. 7 is a block diagram illustrating the configuration of anadaptive filter according to a third embodiment of the presentinvention;

[0022]FIG. 8 is a block diagram illustrating a fifth embodiment of thepresent invention;

[0023]FIG. 9 is a block diagram illustrating the configuration of anadaptive filter according to the fifth embodiment of the presentinvention;

[0024]FIG. 10 is a block diagram illustrating the configuration of acoefficient generator circuit included in the adaptive filter accordingto the fifth embodiment of the present invention;

[0025]FIG. 11 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to the fifthembodiment of the present invention;

[0026]FIG. 12 is a block diagram illustrating the configuration of a tapgroup selection information update circuit included in the tap controlcircuit in the fifth embodiment of the present invention;

[0027]FIG. 13 is a block diagram illustrating the configuration of aninput signal evaluation circuit included in the tap control circuit inthe fifth embodiment of the present invention;

[0028]FIG. 14 is a block diagram illustrating the configuration of aninput signal evaluation circuit according to a sixth embodiment of thepresent invention;

[0029]FIG. 15 is a block diagram illustrating the configuration of aninput signal evaluation circuit according to a seventh embodiment of thepresent invention;

[0030]FIG. 16 is a block diagram illustrating the configuration of aninput signal evaluation circuit according to an eighth embodiment of thepresent invention;

[0031]FIG. 17 is a block diagram illustrating an adaptive filteraccording to a ninth embodiment of the present invention;

[0032]FIG. 18 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to the ninthembodiment of the present invention;

[0033]FIG. 19 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to a tenthembodiment of the present invention;

[0034]FIG. 20 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to an eleventhembodiment of the present invention;

[0035]FIG. 21 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to a twelfthembodiment of the present invention;

[0036]FIG. 22 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to athirteenth embodiment of the present invention;

[0037]FIG. 23 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to afourteenth embodiment of the present invention;

[0038]FIG. 24 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to a fifteenthembodiment of the present invention;

[0039]FIG. 25 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to a sixteenthembodiment of the present invention;

[0040]FIG. 26 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to aseventeenth embodiment of the present invention;

[0041]FIG. 27 is a block diagram illustrating the configuration of anadaptive filter according to an eighteenth embodiment of the presentinvention;

[0042]FIG. 28 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to theeighteenth embodiment of the present invention;

[0043]FIG. 29 is a block diagram illustrating the configuration of astep size generator circuit included in the tap control circuit in theeighteenth embodiment of the present invention;

[0044]FIG. 30 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to anineteenth embodiment of the present invention;

[0045]FIG. 31 is a block diagram illustrating the configuration of anadaptive filter according to a twentieth embodiment of the presentinvention;

[0046]FIG. 32 is a block diagram illustrating the configuration of acoefficient generator circuit included in the adaptive filter accordingto the twentieth embodiment of the present invention;

[0047]FIG. 33 is a block diagram illustrating the configuration of anadaptive filter according to a twenty first embodiment of the presentinvention; and

[0048]FIG. 34 is a block diagram illustrating the configuration of a tapcontrol circuit included in the adaptive filter according to a twentysecond embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0049]FIG. 2 is a block diagram illustrating a first embodiment of thepresent invention. Since FIG. 2 is identical to FIG. 1 which is a blockdiagram of a prior art example except for control circuit 70 andadaptive filters 80, 81, 82, the following description on detailedoperations will be centered on these differences.

[0050] Control circuit 70 receives convergence indexes 601, 603, 605 andinput signal intensities 607, 608, 609 from adaptive filters 80, 81, 82,respectively, and evaluates them. The convergence indexes represent theconvergence degrees of adaptive filters 80, 81, 82, while the inputsignal intensities represent information on the intensities of signalsfed to the respective adaptive filters. In consideration of theconvergence indexes together with the information on the input signalintensities, a predetermined fixed number of coefficient updates isdistributed to each line.

[0051] Assume now that the convergence indexes at time k are μ₁(k),μ₂(k), μ₃(k), respectively. Control circuit 70 first averages them tofind average convergence indexes μ₁bar(k), μ₂bar(k), μ₃bar(k). Whileseveral methods are available for averaging, averaging using afirst-order leaky integration, for example, can be expressed by:

{overscore (μ)}₁(k+1)=γ{overscore (μ)}₁(1−γ)μ₁(k)  (1)

[0052] where γ is a constant which satisfies 0<γ<1.

[0053] On the other hand, averaging using moving average can beexpressed by: $\begin{matrix}{{{\overset{\_}{\mu}}_{1}\left( {k + 1} \right)} = {\frac{1}{N_{A}}{\sum\limits_{j = {k - N_{A} + 2}}^{k + 1}\quad {\mu_{1}(j)}}}} & (2)\end{matrix}$

[0054] where NA is a window length for the moving average. Completelysimilar calculations are made for μ₂bar(k), μ₃bar(k).

[0055] Subsequently, convergence degrees Δμ₁(k), Δμ₂(k), Δμ₃(k) arecalculated for the respective average convergence indexes. Theconvergence degree can be calculated, for example, by: $\begin{matrix}{{\Delta \quad {\mu_{1}(k)}} = \frac{\left| {{{\overset{\_}{\mu}}_{1}(k)} - {{\overset{\_}{\mu}}_{1}\left( {k - 1} \right)}} \right|}{{\overset{\_}{\mu}}_{1}(k)}} & (3)\end{matrix}$

[0056] This means that a variation per unit time is calculated forμ₁(k). Completely similar calculations can be made for μ₂(k), μ₃(k).Since Δμ(k) for each adaptive filter decreases corresponding to theconvergence of coefficients, an adaptive filter presenting smaller Δμ(k)is advanced more in convergence, and therefore can be given a lowerpriority for coefficient update. This means that the coefficient isupdated a less number of times in a fixed time.

[0057] Based on such principles, coefficient update necessities aremanaged for the respective adaptive filters using memories Γ₁(k), Γ₂(k),Γ₃(k), respectively.

[0058] First, Δμ₁(k), Δμ₂(k), Δμ₃(k) are compared with a predefinedthreshold value, and memories Γ₁(k), Γ₂(k), Δ₃(k) are increased forthose larger than the threshold value. Δμ(k) smaller than the thresholdvalue can be regarded as indicating that a coefficient update isadvanced, i.e., the convergence is reached. Therefore, once Δμ(k) fallsacross the threshold value, an associated line is recorded, such thatΓμ(k) is subsequently set to zero at all times for this line.

[0059] Initial values for all the memories are set to zero, and theadaptive filters are started operating. Only when Δμ₁(k), Δμ₂(k), Δμ₃(k)are larger than the threshold value, they are added to the values inmemories Γ(k) associated therewith. For example, when Δμ₁(k) and Δμ₂(k)are larger than the threshold value, operations are performed asfollows:

Γ₁(k+1)=Γ₁(k)+Δμ₁(k)  (4)

Γ₂(k+1)=Γ₂(k)+Δμ₂(k)  (5)

Γ₃(k+1)=Γ₃(k)  (6)

[0060] When k=k_(D), Γ(k) is evaluated before it is reset to zero. Thisevaluation and resetting operation is repeated each time k increases byk_(D). The value of Γ(k) immediately before it is reset draws anupwardly convex trajectory which gradually increases from zero to amaximum associated with an increase in k, and then decreases to zero. Onthe other hand, on each of multiplexed communication lines, it is knownthat calls are generated in accordance with the Poisson distribution. Inother words, each adaptive filter is started operating at a differenttime. Therefore, by conducting such a control, the coefficients can beupdated preponderantly in an adaptive filter which presents a highnecessity for a coefficient update at that time. A total amount ofoperations required for the coefficient updates remains unchanged forall lines, even if the number of adaptive filters is increased.

[0061] On the other hand, when k is an integer multiple of k_(D), anevaluation is made as well on the information on the input signalintensity. Assuming that this value is represented by φ(k), a valuedefined by the following equation can be used as φ(k): $\begin{matrix}{{\varphi (k)} = {\sum\limits_{j = {k - k_{D}}}^{k}\quad {x^{2}(j)}}} & (7)\end{matrix}$

[0062] where x(j) is a j-th sample of input signal x. Specifically, φ(k)is a sum total of squared input signal samples from time k to k-k_(D).Of course, φ(k) may be a sum total of squared input signal samples fromtime k to k-k_(D1).

[0063] Here, 0<k_(D1)<k_(D). Alternatively, a sum total of absoluteinput signal samples may be substituted for the sum total of squaredinput signal samples.

[0064] Further, while φ(k) represents the input signal intensity, noadaptive filter generally updates coefficients when an input signal isclose to zero. It is therefore possible to binarize φ(k) for setting itto one when it exceeds the predefined threshold value and to zerootherwise. Instead of the binarization, multi-value quantization may beperformed. φ(k) thus calculated represents an input signal intensity oneach line.

[0065] Next, φ(k) is calculated as defined by the product of Γ(k) andφ(k). When k is an integer multiple of k_(D), a total number of updatesdetermined by a predefined amount of operations is distributed inaccordance with φ1(k), φ2(k), φ3(k). Also, the values of Γ(k), φ(k) andφ(k) are reset to zero. In this event, if there is a line with Γ(k)equal to zero, this represents that the line does not need to update thecoefficients because the coefficients have converged or an input signalis too small, so that a predefined small number is allocated to allowthe line to follow changes in the system. For the remaining lines, thesmall number is subtracted from a total available number fordistribution to derive the remainder which is allocated thereto.Alternatively, the predefined small number may be allocated only to theline with Γ(k) equal to zero, while the remaining lines may be allocatedbased on the value of φ(k). Since φ(k) is set to a small value or zerofor a line which does not update the coefficients due to a feeble inputsignal, the line is allocated a small number of coefficient updates.

[0066] In other words, no number of coefficient updates is allocated invain. When the total number of coefficient updates permitted to all theadaptive filters is larger than k_(D), a plurality of adaptive filerscan simultaneously update the coefficients. With the number of linesequal to three, it can be readily understood that the amount ofoperations is effectively reduced when the total number of coefficientupdates is 3 k_(D) or less. Further, in any situation, a predefinedsmall number may be first distributed to all lines, and the remaindermay be distributed based on φ(k).

[0067] The simplest example of distribution may be a proportionaldistribution. Alternatively, a weighted proportional distribution isalso possible. The result of such a distribution represents the numberof coefficient update during k_(D) sampling periods, where the valuemust be an integer. Thus, a procedure such as round-down, round-up,round-off or the like is performed for transforming the result of thedistribution into an integer. As a result, the sum total of integervalues allocated to the respective lines can be smaller than an actuallypermitted total number of coefficient updates. This means that a numberof coefficient updates can be further added to some lines. Such aredistribution for a small remainder is also possible by a variety ofmeans. The simplest example is a collective allocation to the line whichpresents maximum values of the aforementioned Γ(k), φ(k), φ(k). Also,when the small remainder is one or more, the value can be againredistributed using a proportional distribution or the like inaccordance with the values of Γ(k), φ(k), φ(k). While a variety ofdistribution methods can be otherwise employed, details thereon isomitted here. Each adaptive filter updates the coefficients inaccordance with the number of coefficient updates allocated thereto. Theoperations performed during k=0-k=k_(D) so far described are repeatedsubsequently each time k increases by k_(D).

[0068] Memories Γ₁(k), Γ₂(k), Γ₃(k) may be controlled based on averagedΔμ₁(k), Δμ₂(k), Δμ₃(k) corresponding to Equation (1) or Equation (2),instead of Δμ₁(k), Δμ₂(k), Δμ₃(k). Also, Δμ(k) may be calculateddirectly using the convergence index μ(k) without averaging inaccordance with Equation (1) or Equation (2). Further, in the foregoingdescription, memories Γ₁(k), Γ₂(k), Γ₃(k) are subjected to an increaseonly when Δμ₁(k), Δμ₂(k), Δμ₃(k) are larger than the predefinedthreshold value. Alternatively, memories Γ₁(k), Γ₂(k), Γ₃(k) can besubjected to an increase for all Δμ₁(k), Δμ₂(k), Δμ₃(k). This means theomission of a determination on convergence and a special operation forallocation of a fixed number in accordance therewith.

[0069] Control circuit 70 supplies coefficient update control signals602, 604, 606, which are determined based on the aforementioned φ(k), atpredefined time intervals corresponding to adaptive filters 80, 81, 82.

[0070] Coefficient update control signals 602, 604, 606 are informationwhich determines how many times the respective adaptive filters updatethe coefficients in the predefined time interval. Coefficient updatestep sizes are selectively set to zero in accordance with these valuesto control the number of coefficient updates.

[0071] It has been described that a plurality of adaptive filters can bepermitted to simultaneously update coefficients when the total number ofcoefficient updates permitted to all the adaptive filters is larger thank_(D). When the total permitted number of coefficient updates is equalto N_(adapt)k_(D), N_(adapt) adaptive filters can be permitted tosimultaneously update coefficients, where N_(adapt) is an integer. Whenthe actual number M of lines is larger than the number N_(adapt) ofadaptive filters which are permitted to simultaneously updatecoefficients, scheduling becomes critical for determining in which orderadaptive filters of which lines are permitted to update coefficients.While the scheduling can be performed in a variety of approaches, anexemplary approach will be described with reference to FIG. 3.

[0072]FIG. 3 is an exemplary procedure for determining a coefficientupdate order schedule for the adaptive filters. A basic procedure isshown below.

[0073] 1. Prepare empty arrays equal to N_(adapt).

[0074] 2. Channel numbers are arranged in the order of the correspondingnumbers of coefficient updates allocated thereto.

[0075] 3. N_(adapt) channels are extracted and placed in the emptyarrays in order of the corresponding allocated number of coefficientallocations, where a size occupied thereby in the array corresponds tothe number of coefficient updates allocated thereto.

[0076] 4. Channels allocated larger numbers of coefficient updates areextracted from the remainder, and placed in arrays in the order reverseto Procedure 3.

[0077] 5. The procedures 3 and 4 are repeated until the remaining numberof channels is reduced to N_(adapt) or less.

[0078] 6. The remaining channels are placed in the arrays in a mannersimilar to before. If the last channel is not accommodated in theremaining space of a single array, it is divided into a plurality ofpieces for accommodation.

[0079] 7. When the last channel is divided into a plurality of pieces,the order of channels within an array is changed such that dividedpieces are not placed at the same position in different arrays.

[0080] A state after the procedure 3 is finished corresponds to State 1in FIG. 3, where CH1 represents Channel 1.

[0081] Here, there are arrays above a dotted line, and remainingchannels CH3, CH5, CH7, CH2 below the dotted line. The result ofexecuting the aforementioned Procedure 4 is State 2. Remaining channelsCH3, CH5, CH7 are placed in arrays in the order reverse to the procedure3 in accordance with the numbers of coefficient updates allocatedthereto. There is also remaining channel CH2 below the dotted line. Whenthe aforementioned procedure 6 is finished, State 3 appears. In State 3,CH2 is located at the same position of the horizontal axis correspondingto the time axis, and coefficients are updated for CH2 a plurality oftimes in the same sampling period. To avoid this, the result ofexecuting the aforementioned procedure 7 is a state labeled “end.” Theorder of CH4, CH3, CH2 is reversed. Therefore, the coefficient updatefor CH2 is distributed to the beginning and the end of k_(D) samplingperiods, so that the coefficient update is not executed a plurality oftimes in the same sampling period.

[0082]FIG. 4 is a block diagram illustrating an exemplary configurationof adaptive filters 80, 81, 82 in FIG. 2. Adaptive filter 80 has N−1delay elements from delay element 201 to delay element 20N−1 fordelaying transmission signal 70, where the total number of taps is Nincluding taps with a delay of zero. On the other hand, for generatingtap coefficients of the adaptive filter, N coefficient generatorcircuits 3101-310N are provided. N delay signals, which are outputs ofthe delay elements, are supplied to coefficient generator circuits3101-310N and multipliers 401-40N corresponding thereto. Multipliers401-40N multiply tap coefficient values delivered from coefficientgenerator circuits 3101-310N by delay signals delivered from the delayelements, respectively, and supply the results to adder circuit 8. Addercircuit 8 adds all multiplication results supplied from multipliers401-40N, and delivers as echo replica 701. Step size control circuit 106supplies coefficient generator circuits 3101-310N with step sizes foruse in the coefficient update through output terminals 8011-801N.

[0083] Step size control circuit 106 sequentially calculate the stepsizes in order to improve noise resistance in coefficient adaptation.Here, noise represents signals other than a difference between the echoand echo replica added to error signal 702, and has been already addedto the echo at received signal input terminal 4 in FIG. 2. This noisemay be a pure noise component such as thermal noise or may be a voice ofa communication party received through 2-4 wire hybrid transformercircuit 3. Such noise components are not related to error signal 702 andtherefore cause an erroneous coefficient update if their power is large.For this reason, if the noise has large power, step size control circuit106 controls the step sizes to be smaller.

[0084] Methods of controlling step sizes for purposes of improving thenoise resistance are described in IEEE PROCEEDINGS OF INTERNATIONALCONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, vol. II,PP.1392-1395, April, 1995 (Reference 4), and IEEE PROCEEDINGS OFINTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING,vol. III, PP.1753-1756, May, 1998 (Reference 5). In the methodsdescribed in these references, a common step size is supplied for allcoefficient generator circuits, and its value μ(k) at time k is givenby: $\begin{matrix}{{\mu (k)} = \frac{\mu_{0}{P_{x}(k)}}{{P_{x}^{2}(k)} + {\alpha^{2}{P_{N}^{2}(k)}}}} & (8)\end{matrix}$

 P _(N)(k+1)=βP _(N)(k)+(1−β)e ²(k)  (9)

[0085] where e(k) is error signal 702, α, β, μ₀ are constants, and

P _(X)(k)=X(k)T _(X)(k)  (10)

[0086] Error signal e(k) is supplied through input terminal 810. VectorX(k) is a column vector, elements of which are delayed signal samplessupplied through input terminals 804 ₀-804 _(N−1). Vector X(k)^(T)represents a transpose of vector X(k). P_(N)(k) is updated when errorsignal 702 has power larger than that of echo replica 701 in Reference4, and when P_(X)(k) is smaller than a predefined threshold value inReference 5. The power of echo replica 701 is supplied as an output ofadder 8 through input terminal 811.

[0087] Step size control circuit 106 has terminal 808 for delivering thestep size as convergence index 601; terminal 802 for deliveringinformation 607 on an input signal intensity; and terminal 809 forreceiving coefficient update control signal 602. P_(X)(k) calculated inaccordance with Equation (10) is delivered as information 607 on theinput signal intensity through terminal 802, while the step sizecalculated in accordance with Equation (8) is delivered as convergenceindex 601 through terminal 808, and both are transferred to controlcircuit 70. Specifically, a limited number of coefficient updates isallocated to respective lines in accordance with the step size and inputsignal power. A line having a small step size can be regarded aspresenting a less necessity for the coefficient update because thecoefficient substantially changes in small amount in the coefficientupdate. Coefficient update control signal 602 received through terminal809 is multiplied by the step size calculated in accordance withEquation (8), and the product is supplied to terminals 801 ₁-801 _(N) asthe step size. Stated another way, the coefficient update is stoppedwhen coefficient update control signal 602 is zero. While the foregoingdescription has been made on the assumption that P_(X)(k) calculated inaccordance with Equation (10) is delivered as information 607 on theinput signal intensity through terminal 802, another amountrepresentative of information on the input signal intensity may be usedinstead of P_(X)(k). Examples of such other amounts include a sum totalof absolute values of delayed signal samples supplied through inputterminals 804 ₀-804 _(N−1), and a maximum value, a median value, aweighted average value, and the like of the delayed signal samples.Alternatively, these may be calculated using some of the delayed signalsamples, as previously described.

[0088] The configuration of coefficient generator circuit 310 _(i) (i=1,2, . . . , N) can be represented as in FIG. 5.

[0089] Error signal 702 is multiplied by the step size in multiplier 31,and further multiplied by delayed signals supplied from delay elements20 ₁-20 _(N−1) in multiplier 32. The output of multiplier 32, whichrepresents the amount of modification to a coefficient, is added to acoefficient value stored in memory circuit 34 in adder 33, and theresult of the addition is fed back to memory circuit 34. The delayedvalue in memory circuit 34 serves as a coefficient value after anupdate.

[0090] While the configuration and operation of adaptive filter 80 havebeen described with reference to the block diagram illustrated in FIG.4, adaptive filters 81 and 82 in FIG. 2 are also completely identical inconfiguration and operation to adaptive filter 80. Further, while FIG. 1has been described for an example in which the number of adaptivefilters is three, similar description applies to the case where thenumber of adaptive filters is three or more.

[0091]FIG. 6 is a block diagram illustrating a second exemplaryconfiguration of adaptive filters 80, 81, 82 in FIG. 2 as a secondembodiment of the present invention. FIG. 6 is identical to FIG. 3 whichillustrates the first exemplary configuration except that step sizecontrol circuit 106 is replaced with step size control circuit 107. Stepsize control circuit 107 differs from step size control circuit 106 inthat the former does not have terminal 811 for receiving the output ofadder 8. This is because step size control circuit 107 differs from stepsize control circuit 106 in the method and purpose of calculating thestep size.

[0092] The control of the step size in step size control circuit 106 isconducted for purposes of improving the noise resistance in the adaptivecontrol for coefficient values, whereas step size control circuit 107sequentially calculates step sizes in order to reduce a convergence timeof coefficients of the adaptive filter. An exemplary method ofcontrolling a step size for such a purpose is described in IEEEPROCEEDINGS OF INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNALPROCESSING, vol. III, PP.1385-1388, April, 1990 (Reference 6).

[0093] In the method described in Reference 6, a common step size issupplied to all coefficient generator circuits, and its value μ(k) attime k is given by:

μ(k)=μ(k−1)+ρe(k)e(k−1)X(k−1)^(T) X(k)  (11)

[0094] where ρ is a positive constant, and e(k) is supplied to inputterminal 810 as error signal 702. Also, elements of vector X(k) aresupplied to input terminals 804 ₀-804 _(N−1) as delayed signals. Thestep size calculated in accordance with Equation (11) is delivered asconvergence index 601 through terminal 808, and transferred to controlcircuit 70 in FIG. 2. In addition, P_(X)(k) calculated in accordancewith Equation (10) is delivered through terminal 802 as information 607on an input signal intensity, and transferred to control circuit 70.Further, coefficient update control signal 602 received through terminal809 is multiplied by the step size calculated in accordance withEquation (11), and the product is supplied to terminals 801 ₁-801 _(N)as the step size. Stated another way, the coefficient update is stoppedwhen coefficient update control signal 602 is zero.

[0095] An algorithm similar to that described in Reference 6 isdescribed in IEEE PROCEEDINGS OF INTERNATIONAL CONFERENCE ON ACOUSTICS,SPEECH AND SIGNAL PROCESSING, vol. III, pp.539-542, April, 1993(Reference 7). This algorithm is identical to the algorithm described inReference 6 except that a nonlinear operation is applied for determininga step size, and can be readily implemented only by changing theoperation in step size control circuit 107.

[0096]FIG. 7 is a block diagram illustrating a third exemplaryconfiguration of adaptive filters 80, 81, 82 in FIG. 2 as a thirdembodiment of the present invention. FIG. 7 is identical to FIG. 6 whichillustrates the second exemplary configuration except that the step sizecontrol circuit 107 is replaced with step size control circuit 108. Stepsize control circuit 108 differs from step size control circuit 107 inthat the former has input terminals 803 ₁-803 _(N) for receivingcoefficient values from the respective coefficient generator circuits,and does not have input terminal 810 for receiving the error signal.This is because step size control circuit 108 differs from step sizecontrol circuit 107 in the method of calculating the step size.

[0097] A step size control method in step size control circuit 108 isdescribed in the proceedings of Fall National Convention of theInstitute of Electronics, Information and Communication Engineers ofJapan, Vol. 1, September, 1991, pp.1-75 (Reference 8). In this method, acommon step size is supplied to all coefficient generator circuits, andits value μ(k) at time k is given by: $\begin{matrix}{{\mu (k)} = {\delta \cdot \frac{{STA}\left\lfloor {\sum\limits_{j = 0}^{N - 1}\quad c_{j}^{2}} \right\rfloor}{{LTA}\left\lfloor {\sum\limits_{j = 0}^{N - 1}\quad c_{j}^{2}} \right\rfloor}}} & (12)\end{matrix}$

[0098] where δ is a positive constant, and coefficients c_(j) aresupplied from coefficient generator circuits through input terminals 803₁-803 _(N). STA[•] and LTA[•] represents a short time average and a longtime average, respectively, of the arguments, and can be calculated inthe same form as Equation (1) or Equation (2). The step size calculatedin accordance with Equation (12) is delivered as convergence index 601through terminal 808, and transferred to control circuit 70 in FIG. 2.In addition, P_(X)(k) calculated in accordance with Equation (10) isdelivered through terminal 802 as information 607 on an input signalintensity, and transferred to control circuit 70. On the other hand,coefficient update control signal 602 received through terminal 809 ismultiplied by the step size calculated in accordance with Equation (12),and the product is supplied to terminals 801 ₁-801 _(N) as the stepsize.

[0099] Stated another way, the coefficient update is stopped whencoefficient update control signal 602 is zero. While a variety ofcoefficient update step size control circuits have been described withreference to FIGS. 4 to 7, the present invention can be applied incompletely the same manner to step size control circuits other thanthose. Such methods of controlling a time-varying step size aredescribed in IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 45, NO.3,PP.631-639, March, 1997 (Reference 9), IEEE PROCEEDINGS OF DIGITALSIGNAL PROCESSING WORKSHOP, PP.#82, AUGUST, 1998 (Reference 10), theJournal of Acoustical Society of Japan, VOL. 53, NO. 12, PP.941-948,December, 1997 (Reference 11), and the like.

[0100] While the foregoing description has been described on theassumption that all adaptive filters 80, 81, 82 have a time-varying stepsize, the number of coefficient updates can also be distributed insimilar principles when they have a fixed step size. For example, as afourth embodiment of the present invention, a fourth exemplaryconfiguration of adaptive filters 80, 81, 82 can be created by modifyingthe operation of step size control circuit 108 in the adaptive filter ofFIG. 7.

[0101] In the fourth exemplary configuration, coefficient values fedthrough input terminals 803 ₁-803 _(N) are evaluated to reveal theconvergence degrees of the adaptive filters. This is because acoefficient value approaches to a constant value and saturates there asan adaptive filter converges to a larger extent. For this reason, a sumtotal of squared coefficients: $\begin{matrix}{\sum\limits_{j = 0}^{N - 1}\quad c_{j}^{2}} & (13)\end{matrix}$

[0102] can be used as an index for the convergence degree.Alternatively, a sum total of absolute coefficients may be used insteadof the sum total of squared coefficients. Further, variations to thesemay be used such as a partial sum of squared coefficients or a partialsum of absolute coefficients. As a special case of a partial sum, asquared or an absolute maximum coefficient value may be used as an indexto the convergence degree. Information on these coefficient values andinformation on an input signal intensity derived from delayed signalsfed through input terminals 804 ₁-804 _(N) are both supplied to controlcircuit 70 through output terminals 808, 802, respectively, therebymaking it possible to achieve an optimal distribution of the number ofcoefficient updates.

[0103] In the foregoing description, the adaptive filter is a standardtransversal type. However, it is known that an echo canceler applied tosatellite links and the like has a number of coefficient generatorcircuits less than the total number of delay elements, and that anadaptive filter for dynamically controlling connections of the delayelements with the coefficient generator circuits can accomplish a moreefficient implementation. The following description will be made on anembodiment which employs such adaptive filters.

[0104]FIG. 7 is a block diagram illustrating a fifth embodiment of thepresent invention. The fifth embodiment differs from the firstembodiment illustrated in FIG. 2 in that adaptive filters 80, 81, 82 arereplaced with adaptive filters 83, 84, 85, and control circuit 70 isreplaced with control circuit 71. Each of adaptive filters 83, 84, 85 isan adaptive filter which adaptively controls tap positions. Controlcircuit 71 receives tap position information 611, 613, 615 from adaptivefilters 83, 84, 85 instead of convergence indexes 601, 603, 605, andevaluates them together with input signal intensities 607, 608, 609.

[0105] Assume now that the tap position information at time k isrepresented by λ₁(k), λ₂(k), λ₃(k), respectively. Control circuit 71first averages them to find average tap position information λ₁bar(k),λ₂bar(k), λ₃bar(k). The averaging can be performed in accordance with:

{overscore (λ)}₁(k+1)=γ{overscore (λ)}₁(k)+(1−γ)λ₁(k)  (14)

or $\begin{matrix}{{{\overset{\_}{\lambda}}_{1}\left( {k + 1} \right)} = {\frac{1}{N_{A}}{\sum\limits_{j = {k - N_{A} + 2}}^{k + 1}\quad {\lambda_{1}(j)}}}} & (15)\end{matrix}$

[0106] in a similar manner to Equation (1) or Equation (2). Completelysimilar calculations are made for λ₂bar(k), λ₃bar(k). Subsequently,convergence degrees Δλ₁(k), Δλ₂(k), Δλ₃(k) are calculated for therespective average tap position information. The convergence degree canbe calculated, for example, by: $\begin{matrix}{{\Delta \quad {\lambda_{1}(k)}} = \frac{\left| {{{\overset{\_}{\lambda}}_{1}(k)} - {{\overset{\_}{\lambda}}_{1}\left( {k - 1} \right)}} \right|}{{\overset{\_}{\lambda}}_{1}(k)}} & (16)\end{matrix}$

[0107] This means that a variation per unit time is calculated forΔλ₁(k). Completely similar calculations can be made for Δλ₂(k), Δλ₃(k).Since Δλ(k) for each adaptive filter decreases corresponding to theconvergence of coefficients, an adaptive filter presenting smaller Δλ(k)is advanced more in convergence, and therefore can be given a lowerpriority for coefficient update. This means that the coefficients areupdated a less number of times in a fixed time. Based on suchprinciples, coefficient update necessities are managed for therespective adaptive filters using memories Γ₁(k), Γ₂(k), Γ₃(k),respectively. Since the management of the coefficient update necessitiesfor the respective adaptive filters using Γ(k) is completely the same asthe first embodiment of the present invention described in connectionwith FIG. 2, description thereon is omitted. The description in thefirst embodiment can be applied as it is by changing μ to λ and the stepsize to the tap position information.

[0108] When k is an integer multiple of k_(D), an evaluation is made aswell on the information on the input signal intensity, and φ(k) iscalculated by the method described in connection with FIG. 2. Next, φ(k)is calculated as defined by the product of Γ(k) and φ(k). Controlcircuit 71 uses φ(k) thus calculated to determine coefficient updatecontrol signals 602, 604, 606 in a completely similar method to controlcircuit 70. At predefined time intervals, coefficient update controlsignals 602, 604, 606 determined based on the above-mentioned φ(k) aresupplied to adaptive filters 83, 84, 85. Coefficient update controlsignals 602, 604, 606 supplied from control circuit 71 are completelyidentical to the coefficient update control signals supplied fromcontrol circuit 70.

[0109]FIG. 9 is a block diagram illustrating a first exemplaryconfiguration of adaptive filters 83, 84, 85 in FIG. 8. Unlike FIGS. 4to 7 corresponding to the first to fourth exemplary configurations, inFIG. 9, the position of dispersive regions except for fixed delays areestimated from an impulse response of an echo path, and the location ofcoefficients is adaptively controlled such that tap coefficients of theadaptive filters are located near the estimated dispersive regions. Inparticular, a convergence time is reduced by first estimating anapproximate position of the dispersive region, and placing the tapcoefficients only in the vicinity thereof. Though similar to thatdescribed in Proceedings of Symposium on Digital Signal Processing ofthe Institute of Electronics, Information and Communication Engineers ofJapan, pp. 543-548, November 1997 (Reference 12), this method differs inthat tap control circuit 91 comprises output terminal 906 for extractingtap position information 611 to the outside, output terminal 909 forextracting information 607 on the input signal intensity to the outside,and input terminal 907 for receiving coefficient update control signal602. In the following, the configuration and operation of adaptivefilter 83 will be described with reference to the figure.

[0110] The adaptive filter illustrated in FIG. 9 has N−1 delay elementsfrom delay element 20 ₁ to delay element 20 _(N−1) for delayingtransmission signal 700, where the total number of taps is N includingtaps with a delay of zero. On the other hand, for generating tapcoefficients of the adaptive filter, L coefficient generator circuits 30₁-30 _(L) are provided. The total number N of taps and the number L ofcoefficient generator circuits of the adaptive filter is in arelationship expressed by N>L. Specifically, unlike the standardadaptive FIR filter, the adaptive FIR filter illustrated in FIG. 8comprises a number of tap coefficients sufficient to cover a substantialdispersive regions except for fixed delay sections, and adaptivelylocates the tap coefficients around the dispersive regions.

[0111] For this purpose, the adaptive filter has path switch 7 forswitching connections between the outputs of the delay elements and thecoefficient generator circuits, and has tap control circuit 91 forpurposes of controlling this path switch 7.

[0112] Path switch 7 operates to select outputs of L delay elements fortransmission to the coefficient generator circuits based on a tapposition control signal supplied from output terminal 900 of tap controlcircuit 91. L delay signals, which are the outputs of path switch 7, aresupplied to coefficient generator circuits 30 ₁-31 _(L) and multipliers40 ₁-40 _(L) corresponding thereto. Multipliers 40 ₁-40 _(L) multiplytap coefficient values delivered from coefficient generator circuits 30₁-30 _(L) by the delayed signals delivered from path switch 7respectively, and supply the results to adder circuit 8. Adder circuit 8adds all multiplication results supplied from multipliers 40 ₁-40 _(L),and delivers as echo replica 701.

[0113] Tap control circuit 91 supplies a step size through outputterminals 901 ₁-901 _(L) for use by coefficient generator circuits 30₁-31 _(L) in the event of coefficient update. A coefficient clear signalis also supplied to coefficient generator circuits 30 ₁-30 _(L) throughoutput terminals 902 ₁-902 _(L) of tap control circuit 91, and used forresetting coefficients to zero. On the other hand, tap control circuit91 receives coefficient values generated by coefficient generatorcircuits 30 ₁-30 _(L) through input terminals 903 ₁-903 _(L), and usesthe coefficient values for generating the tap position control signal,step size, and coefficient clear signal. Tap control circuit 91 alsoreceives an input of delay element 20 ₁ and outputs of 20 ₁-20 _(N−1)through input terminals 904 ₀-904 _(N−1), and delivers results ofevaluating them through output terminal 909 as information 607 on theinput signal intensity.

[0114] Assuming now the LMS algorithm described in Reference 1 as acoefficient update algorithm, value c_(i)(k+1) at the (k+1)th update ofthe i-th coefficient is given using value c_(i)(k) at the k-th updateby:

c _(i)(k+1)=c _(i)(k)+μ_(i) e(k)x(k−a(i))  (17)

[0115] where i is a step size for the i-th coefficient, e(k) is aresidual echo, x(k−a(i)) is an input signal sample at the (k−a(i))thcoefficient update. a(i) is a set which is composed of indexes to thedelay elements selected by path switch 7, and the number of elements isL.

[0116] In this event, the configuration of coefficient generator circuit30 _(i) (i=1, 2, . . . , L) can be represented as in FIG. 9. While FIG.9 is basically identical in configuration to coefficient generatorcircuit 300 _(i) illustrated in FIG. 4, it has a function of forcingcoefficient values held in memory circuit 34 to zero when thecoefficient clear signal is supplied thereto from tap control circuit 9through output terminal 902 _(i) (i=1, 2, . . . , L).

[0117] As is apparent from the foregoing description, tap coefficientsof the adaptive filter are connected only to some of the delay elementsselected by path switch 7. In the following, a tap having a connectedtap coefficient is called the active tap, while a tap not having aconnected tap coefficient is called the inactive tap. In the actualadaptive tap coefficient location, tap coefficients less than the actualtotal number of taps are located, for example, with equal intervals, asinitial locations. These are active taps, whereas taps withoutcoefficients located therein are inactive taps. Alternatively, theactive taps may be initially located from the first one in theincreasing order of the tap indexes, or may be given at random.

[0118]FIG. 11 is a block diagram illustrating the configuration of tapcontrol circuit 91. A group of memory circuits 110 ₁, 110 ₂, . . . , 110_(M) have a FIFO (First-In-First-Out) structure of a length N/M forstoring N−L inactive tap numbers. Inactive taps are divided into groups,each of which is comprised of N/M tap numbers derived by equallydividing all taps by M, and are separately stored therein. This group iscalled the tap group. For example, when the total number N of taps is20, and the number M of tap groups is 5, the number N/M of tapsbelonging to each tap group is 4. Also, the tap group is labeled G(n)(n=1, 2, . . . , 5), and tap numbers belonging to G(n) are indicated inbraces as follows:

[0119] G(1)={1, 2, 3, 4}

[0120] G(2)={5, 6, 7, 8}

[0121] G(3)={9, 10, 11, 12}

[0122] G(4)={13, 14, 15, 16}

[0123] G(5)={17, 18, 19, 20}

[0124] Among these numbers, those currently classified as inactive arestored in corresponding memory circuits. In the foregoing example,elements of G(n) (n=1, 2, . . . , 5) are stored in 110 _(n).

[0125] Selector circuit 112 selects any of memory circuits 110 ₁, 110 ₂,. . . , 110 _(M) in response to a tap group selection signal suppliedfrom memory circuit 150 at every Q coefficient updates, and extracts thetap index stored at the head of a queue for transfer to memory circuit114 as a new active tap index. Memory circuit 114, which stores L activetap numbers not included in memory circuits 110 ₁, 110 ₂, . . . , 110_(M), supplies an active tap index to output terminal 900 as a tapposition control signal. Active tap indexes in an initial state, i.e.,initially set values in memory circuit 114 may be tap indexes arrangedin an arbitrary order. For example, L indexes may be set in theincreasing order of tap indexes, or L indexes may be selected and set atrandom. As an example, consider that L taps are selected in theincreasing order from among all tap indexes. In the previous example,all tap indexes are 1, 2, 3, . . . , 20.

[0126] In this event, assuming that the index L of active taps is equalto 3, and the index N−L of invalid taps is equal to 17, three taps 1, 2,3 from the smallest one are selected for active tap indexes and are heldin memory circuit 114 as initial values. Initial values for memorycircuits 110 ₁, 110 ₂, . . . , 110 _(M) are chosen to be tap indexesother than the initial values set in memory circuit 114. In theforegoing example, 4, 5, 6, . . . , 20 except for 1, 2, 3 are selectedfor the initial values which are stored in corresponding memory circuitsof memory circuits 110 ₁, 110 ₂, . . . , 110 _(M). The foregoing initialsetting is followed by coefficient updates for the active taps selectedby path switch 7. The active taps are updated after every Q coefficientupdates (Q is a positive integer), and the location of the coefficientsis changed. The active taps are updated in the following procedure.

[0127] Minimum coefficient detector circuit 116 receives the active tapindexes delivered from memory circuit 114, and outputs of the respectivecoefficient generator circuits supplied to input terminals 903 ₁-903_(L), i.e., tap coefficients, and detects an active tap indexcorresponding to a coefficient which has a minimum absolute value. Thedetected active tap index is supplied to memory circuit 114,distribution circuit 118, evaluation circuit 120, and coefficient clearcircuit 122.

[0128] Coefficient clear circuit 122 generates a coefficient clearsignal for a coefficient generator circuit corresponding to the suppliedtap index, and transfers this to any of corresponding output terminals902 ₁-902 _(L). This coefficient clear signal is supplied to acorresponding coefficient generator circuit for setting coefficients tozero. Evaluation circuit 120 calculates a tap group to which the tapindex supplied from minimum coefficient detector circuit 116 belongs,and transfers a corresponding tap group index to distribution circuit118.

[0129] Distribution circuit 118 selects a memory circuit correspondingto the tap group index supplied from evaluation circuit 120 from amongmemory circuits 110 ₁, 110 ₂, . . . , 110 _(M), and transfers a tapindex having the minimum coefficient supplied from minimum coefficientdetector circuit 116. The transferred tap index is stored in memorycircuit 110 ₁ specified by distribution circuit 118. Memory circuit 114deletes the tap index supplied from minimum coefficient detector circuit116 from stored contents, and stores the new active tap index suppliedfrom selector circuit 112, thereby updating active tap indexes storedtherein.

[0130] Coefficient value evaluation circuit 130 receives tap coefficientvalues delivered from the respective coefficient generator circuits, andthe active tap index delivered from memory circuit 114, and calculates asum total of absolute coefficient values for each tap group. These M sumtotals of the absolute coefficient values are rearranged according tothe magnitude, and corresponding tap group indexes are transferred totap group selection information update circuit 140 as an “order.”

[0131] Coefficient value evaluation circuit 130 also transfers the sumtotals of the absolute coefficient values to tap group selectioninformation update circuit 140 as “coefficient sums.” Tap groupselection information update circuit 140 calculates an order in whichthe tap groups are selected, based on the information, and transmits theresult to memory circuit 150 as a “selection order.” Memory circuit 150stores the tap group indexes rearranged in the “selection order”supplied from tap group selection information update circuit 140, in theorder in which they are selected, and supplies the tap group indexes toselection circuit 112 in order. Initial values for the tap group indexesset in memory circuit 150 can be tap group indexes which are arbitrarilyarranged. For example, the tap group indexes may be set in theincreasing order, or may be set at random. Specifically, when the tapgroup indexes held in memory circuit 150 are represented by Z(n) (n=1,2, . . . , M):

[0132] Z(1)=1

[0133] Z(2)=2

[0134] Z(3)=3

[0135] Z(4)=4

[0136] Z(5)=5

[0137] are set as initial values when the tap group indexes are set inthe increasing order in the previous example. Also, an initial value foran address pointer for defining a data read position in memory circuit150 is set at the beginning, and is delivered to selector circuit 112,so that the first tap group index, i.e., Z(1)=1 in the foregoingexample, is delivered to selector circuit 112 as the initial value.

[0138] Upon receipt of this tap group selection signal, selector circuit112 first selects memory circuit 1101, extracts the tap index numberstored at the beginning thereof for transfer to memory circuit 114. Theread address pointer is changed by a “change signal” supplied from tapgroup selection information update circuit 140. Each time the “changesignal” is supplied from tap group selection information update circuit140, memory circuit 150 advances the read address pointer by one for thestored tap groups.

[0139] Coefficient value evaluation circuit 130 takes absolute values ofcoefficients supplied thereto, and sums them up for each tap group.Coefficient value evaluation circuit 130 calculates the ratio of maximumvalue C_(max) of sum totals of absolute coefficient values for each tapgroup to a sum total of absolute coefficient values in each tap group.For example, assuming that the sum total of the absolute coefficientvalues in each tap group is c_(j,max) (1≦j≦M) when the number of tapgroups is M, the ratio R_(j)=c_(j,max)/C_(max) is calculated thereforand transferred to step size generator circuit 160. A similar result canalso be provided when the grand sum of the sum totals of the absolutecoefficient values in each tap group is defined as C_(max). Step sizegenerator circuit 160 generates a step size using R_(j) supplied fromcoefficient value evaluation circuit 130, and transfers the step size tocorresponding output terminal 901 _(i) (i=1, . . . , L). Step size μ_(j)is calculated in accordance with μ_(j)=μ×R_(j) from the result of amultiplication of R_(j) by a predefined constant.

[0140] A correspondence relationship between j and i (1≦i≦L) iscalculated using a tap position control signal supplied from memorycircuit 114 such that a step size used for updating coefficientsbelonging to an j-th tap group is equal to μ_(j). This method ofcalculating the step size permits a larger step size with whichcoefficients are updated in a tap group having large absolutecoefficient values, resulting in a reduction in the convergence time ofthe adaptive filter. On the other hand, coefficient update controlsignal 602 received through input terminal 907 is multiplied by μ_(j),and the product is supplied to output terminals 901 ₁-901 _(N) as anactual step size. In other words, the coefficient update is stopped whencoefficient update control signal 602 is zero. The step sizes suppliedto output terminals 901 ₁-901 _(N) are transferred to correspondingcoefficient generator circuits 30 _(i).

[0141] Maximum value detector circuit 180 receives the “coefficient sum”and “order” from coefficient value evaluation circuit 130, and selects amaximum coefficient sum for transfer to output terminal 906.Specifically, the maximum coefficient sum is transferred to controlcircuit 71 in FIG. 8 as tap position information. Step size generatorcircuit 160 also receives step size control signal 602 through inputterminal 907, and multiplies this by μ_(j). Therefore, the coefficientupdate is stopped when step size control signal 602 is zero.

[0142]FIG. 12 is a block diagram illustrating the configuration of tapgroup selection information update circuit 140.

[0143] The “coefficient sum” supplied from coefficient value evaluationcircuit 130 is transferred to continuous selection time calculationcircuit 1401. Continuous selection time calculation circuit 1401calculates a time for which each tap group is continuously selected inselector circuit 112 based on the “coefficient sum.” Specifically, thesetting is made such that a tap group having a larger sum total ofabsolute coefficient values is given a longer continuous selection time,and new active taps are set intensively in that tap group. For example,assuming in the previous example that the continuous selection time of aj-th tap group is T_(j) (j=1, 2, 3, 4, 5), T_(j) can be expressed by:$\begin{matrix}{T_{j} = {{\frac{A_{j}}{A_{\max}} \cdot \left( {T_{\max} - T_{\min}} \right)} + T_{\min}}} & (18)\end{matrix}$

[0144] as described in Reference 11. Here, A_(j), A_(max), T_(max),T_(min) are a sum total of absolute coefficient values in the j-th tapgroup, a maximum value of sum totals of absolute coefficient values inrespective tap groups, and a maximum value and a minimum value of thetap group continuous selection times, respectively. Specifically, thecontinuous selection time for a tap group having the minimum sum totalof absolute coefficient values is determined to be T_(min); thecontinuous selection time for a tap group having the maximum sum totalof absolute coefficient values is determined to be T_(max); and thecontinuous selection times for other tap groups are determinedcorresponding to the sum totals of absolute coefficient values.

[0145] Generally, T_(j) is represented by the number of coefficientupdates, and this value is transferred to counter 1402. Counter 1402,which is a counter for counting the number of coefficient updates,supplies counter 1403 with a read address change signal each time thenumber of coefficient updates reaches T_(j), and simultaneouslytransfers the read address change signal to memory circuit 150. Counter1403 counts up each time the read address change signal is suppliedthereto from counter 1402, transfers a signal to switch 1404 to instructa change in a tap group selection order when it counts up to the totalnumber M of tap groups, and resets the counted value to zero. Switch1404 closes the circuit upon receipt of the signal instructing the sameto change the tap group selection order, and delivers the tap groupindexes supplied as the “order” from coefficient value evaluationcircuit 130 in the order in which they are supplied thereto as a “tapgroup selection order.” The delivered signals are written from the firstaddress of memory circuit 150, and this write operation changes theorder in which the tap group indexes held in memory circuit 150 areselected.

[0146] Input signal evaluation circuit 170 is supplied with input signalsamples at the input of delay element 201 and at the outputs of 20 ₁-20_(N−1) through input terminals 904 ₀-904 _(N−1). Input signal evaluationcircuit 170 uses these input signal samples to evaluate input signalpower. When the evaluated input signal power is smaller than a firstpredefined threshold value, input signal evaluation circuit 170 deliversa coefficient update stop signal. This coefficient update stop signal istransferred to step size generator circuit 160 and used for setting allstep sizes to zero. Therefore, the step size transferred to coefficientgenerator circuits 30 ₁-30 _(L) through output terminals 901 ₁-901 _(L)is zero in such a case. In other words, though a coefficient updateoperation is performed, no coefficients are actually updated.

[0147] Input signal evaluation circuit 170 also feeds a tap positionupdate stop signal when the evaluated input signal power is smaller thana second predefined threshold value. This tap position update stopsignal is transferred to memory circuit 114, coefficient valueevaluation circuit 130, tap group selection information update circuit140, and minimum coefficient detector circuit 116, and used for stoppinga tap position update. Upon receipt of the tap position update stopsignal, memory circuit 114 stops an operation for replacing a tap indexsupplied from minimum coefficient detector circuit 116 with a tap indexsupplied from selector circuit 112. Upon receipt of the tap positionupdate stop signal, coefficient value evaluation circuit 130 stops thecalculations of the “coefficient sum” and “order” as well as thetransfer of them to tap group selection information update circuit 140.

[0148] Upon receipt of the tap position update stop signal, tap groupselection information update circuit 140 stops updating tap groupselection information. Upon receipt of the tap position update stopsignal, minimum coefficient detector circuit 116 stops detecting a tapindex corresponding to a coefficient having a minimum absolute value,and transferring the detected index to memory circuit 114, evaluationcircuit 120, distribution circuit 118, and coefficient clear circuit122. A sequence of these stop operations results in stopping the updateof the tap position.

[0149] Input signal evaluation circuit 170 also transfers the valueitself of the evaluated input signal power to output terminal 909. Thisvalue is supplied to control circuit 71 and used for allocating thenumber of coefficient updates.

[0150]FIG. 13 is a block diagram illustrating the configuration of inputsignal evaluation circuit 170. Input signal samples at the input ofdelay element 201 and the outputs of 20 ₁-20 _(N−1) supplied to inputsignal evaluation circuit 170 are all squared in square circuits 1701₀-1701 _(N−1), and supplied to adder circuit 1704. Adder circuit 1704adds all the squared input signal samples to find input signal powerwhich is transferred to comparator circuit 1706 and comparator circuit1708. Comparator circuit 1706 and comparator circuit 1708 compare theinput signal power supplied from adder circuit 1704 with a firstthreshold value supplied from memory circuit 170 and a second thresholdvalue supplied from memory circuit 1709, respectively. When the inputsignal power is smaller than the first threshold value, the tap positionupdate stop signal is delivered as an output of comparator circuit 1706.When the input signal power is smaller than the second threshold value,the coefficient update stop signal is delivered as an output ofcomparator circuit 1708.

[0151] Also, the calculated input signal power is delivered as it is foruse as information on the input signal intensity.

[0152] While the configuration and operation of adaptive filter 83 havebeen so far described with reference to FIG. 9, adaptive filters 84 and85 in FIG. 8 are completely identical in configuration and operation toadaptive filter 83. Further, while FIG. 8 has been described for anexample in which the number of adaptive filters is three, the exactlysame description can be applied to the case where the number of adaptivefilters is three or more.

[0153] A sixth embodiment of the present invention employs input signalevaluation circuit 171 instead of input signal evaluation circuit 170 intap control circuit 91 of FIG. 11. Input signal evaluation circuit 171uses input signal samples to evaluate absolute values of input signals.When a sum total of absolute values of the evaluated input signals issmaller than a first predefined threshold value, input signal evaluationcircuit 171 delivers the coefficient update stop signal. Input signalevaluation circuit 171 also delivers the tap position update stop signalwhen the sum total of the absolute values of the evaluated input signalsis smaller than a second predefined threshold value. Input signalevaluation circuit 171 further transfers the sum total of the absolutevalues of the evaluated input signals to output terminal 909. This valueis supplied to control circuit 71 and used for allocating the number ofcoefficient updates.

[0154]FIG. 14 is a block diagram illustrating input signal evaluationcircuit 171 in detail. A difference between input signal evaluationcircuit 171 and input signal evaluation circuit 170 lies in that squarecircuits 1701 ₀-1701 _(N−1) in input signal evaluation circuit 170 areall replaced with absolute value circuits 1702 ₀-1702 _(N−1).Specifically, signals supplied to adder circuit 1704 are not squaredvalues of input signal samples but are absolute values of the same.Therefore, adder circuit 1704 adds all the absolute values of the inputsignal samples to find a sum total of absolute values of the inputsignals which is transferred to comparator circuit 1706 and comparatorcircuit 1708. The sum total of the absolute values of the evaluatedinput signals is also delivered as it is, and utilized as information onthe input signal intensity.

[0155] Since the configuration and operation other than the foregoingare identical to those of input signal evaluation circuit 170,description thereon is omitted.

[0156] The seventh embodiment of the present invention employs inputsignal evaluation circuit 172 instead of input signal evaluation circuit170 in tap control circuit 91 of FIG. 11. Input signal evaluationcircuit 172 holds the coefficient update stop signal and tap positionupdate stop signal generated in the same configuration and operation asinput signal evaluation circuit 170 for a predefined time, and thenreleases the signals. By this holding operation, a coefficient updateand a tap position update are stopped for a while after the coefficientupdate stop signal and tap position update stop signal are delivered.Input signal evaluation circuit 172 also transfers the evaluated inputsignal power to output terminal 909. This value is supplied to controlcircuit 71 and used for allocating the number of coefficient updates.

[0157]FIG. 15 is a block diagram illustrating input signal evaluationcircuit 172 in detail. A difference between input signal evaluationcircuit 172 and input signal evaluation circuit 170 illustrated in FIG.13 lies in that output signals of comparator circuit 1706 and comparatorcircuit 1708 are further processed in multiplier circuit 1732, memorycircuit 1736, counter 1735, switch 1733, delay element 1734, anddemultiplexer circuit 1737. The coefficient update stop signal deliveredfrom comparator circuit 1706 and the tap position update stop signaldelivered from comparator circuit 1708 are supplied to multiplexercircuit 1732. Multiplexer circuit 1732 multiplexes the coefficientupdate stop signal and tap position update stop signal to generate amultiplexed signal which is supplied to one input terminal of switch1733 and to counter 1735. The other input terminal of switch 1733 is fedback with an output signal of switch 1733 through delay element 1734.Specifically, the output of switch 1733 is held when switch 1733 selectsthis feedback path, and a new multiplexed signal is delivered when itselects the other input terminal. Demultiplexer circuit 1737 receivesthe output of switch 1733, demultiplexes this into the coefficientupdate stop signal and tap position update stop signal, and thendelivers them in separation. Switch 1733 is controlled by counter 1735.

[0158] Counter 1735 resets a count as it is supplied with themultiplexed signal from multiplexer circuit 1732, and starts countingup. Also, counter 1735 simultaneously switches the path such that switch1733 selects and delivers a feedback signal supplied from delay element1734. The count-up is performed with a clock which has a frequency equalto the sampling frequency of the input signal. Counter 1735 delivers aswitching signal when the count value is equal to a value supplied frommemory circuit 1736. Upon receipt of the switching signal from counter1735, switch 1733 switches the path to select and deliver themultiplexed signal supplied from multiplexer circuit 1732. Also, theevaluated input signal power is delivered as it is, and utilized asinformation on the input signal intensity. Since the configuration andoperation other than the foregoing are identical to those of inputsignal evaluation circuit 170, description thereon is omitted.

[0159] An eighth embodiment of the present invention uses input signalevaluation circuit 173 instead of input signal evaluation circuit 172 intap control circuit 91 of FIG. 11. Input signal evaluation circuit 173uses input signal samples to evaluate absolute values of input signals.When a calculated sum total of the absolute values of the input signalsis smaller than a first predefined threshold value, input signalevaluation circuit 173 delivers a coefficient update stop signal. Also,when the calculated sum total of the absolute values of the inputsignals is smaller than a second predefined threshold value, inputsignal evaluation circuit 173 delivers a tap position update stopsignal. Input signal evaluation circuit 173 further transfers thecalculated sum total of the absolute values of the input signals tooutput terminal 909. This value is supplied to control circuit 71, andused for allocating the number of coefficient updates.

[0160]FIG. 16 is a block diagram illustrating input signal evaluationcircuit 173 in detail. A difference between input signal evaluationcircuit 173 and input signal evaluation circuit 172 lies in that squarecircuits 1701 ₀-1701 _(N−1) in input signal evaluation circuit 172 areall replaced with absolute value circuits 1702 ₀-1702 _(N−1).Specifically, signals supplied to adder circuit 1704 are not squaredvalues of input signal samples but are absolute values of the same.

[0161] Therefore, adder circuit 1704 adds all the absolute values of theinput signal samples to find a sum total of absolute values of the inputsignals which is transferred to comparator circuit 1706 and comparatorcircuit 1708. The sum total of the absolute values of the evaluatedinput signals is also delivered as it is and utilized as information onthe input signal intensity.

[0162] Since the configuration and operation other than the foregoingare identical to those of input signal evaluation circuit 170,description thereon is omitted.

[0163] In FIGS. 15 and 16, the coefficient update stop signal and tapposition update stop signal are multiplexed to generate a multiplexedsignal which is supplied to one input terminal of switch 1733.Alternatively, they may be independently supplied to one input terminalof switch 1733 without being multiplexed. In this event, multiplexercircuit 1732 and demultiplexer circuit 1737 are not required, whereasother circuits are newly required for holding these stop signals in theexactly same configuration as memory circuit 1736, counter 1735, switch1733, and delay element 1734.

[0164] In the foregoing description, the inputs to input signalevaluation circuit 170, input signal evaluation circuit 171, inputsignal evaluation circuit 172, and input signal evaluation circuit 173are all processed and added in adder circuit 1704. Alternatively, aconfiguration may be possible for adding only some of them. For example,adder circuit 1704 comprised in input signal evaluation circuit 170 mayadd outputs of square circuits 1701 ₀-1701 _(K−1) instead of 1701 ₀-1701_(N−1), and deliver the sum, where k is a positive integer smaller thanN. Alternatively, instead of the outputs of square circuits 1701 ₀-1701_(N−1), outputs of 1701 _(K)-1701 _(N−1) may be added and delivered.Further alternatively, instead of the outputs of square circuits 1701₀-1701 _(N−1), k arbitrary outputs may be selected from 1701 ₀-1701_(N−1), and added, followed by delivery of the sum.

[0165] As an example, assume that adder circuit 1704 comprised in inputsignal evaluation circuit 172 adds outputs of square circuits 1701₀-1701 _(N/M−1) instead of 1701 ₀-1701 _(N−1). These are input signalsamples supplied to delay elements corresponding to the first tap group.These samples are evaluated in input signal evaluation circuit 172,thereby making it possible to promptly detect that a silent section hasreached a tapped delay line comprised of delay elements 20 ₁-20 _(N−1).Upon detection of the arrival of the silent section, the coefficientupdate stop signal and tap position update stop signal are held for atime defined by a value stored in memory circuit 1736, so that thecoefficient update and tap position update can be stopped until thesilent section passes through the tapped delay line. In this event, thevalue stored in memory circuit 1736 is a value slightly larger than Nwhich is equal to the total number of delay elements.

[0166]FIG. 17 is a block diagram illustrating a ninth embodiment of thepresent invention. A difference between the fifth embodiment and ninthembodiment lies in that tap control circuit 91 in FIG. 11 is replacedwith tap control circuit 92 in FIG. 17. Tap control circuit 91 evaluatesan input of delay element 20 ₁ and outputs of 20 ₁-20 _(N−1) receivedthrough input terminals 904 ₀-904 _(N−1) to stop a coefficient updateand a tap position update, whereas tap control circuit 92 evaluatesinput signal samples corresponding to active taps received through inputterminals 905 ₁-905 _(L) to stop the coefficient update and tap positionupdate. For this purpose, input terminals 905 ₁-905 _(L) of tap controlcircuit 92 are supplied with input signal samples corresponding toactive taps.

[0167]FIG. 18 is a block diagram illustrating the configuration of tapcontrol circuit 92. Since tap control circuit 92 is identical to FIG. 11which is a block diagram of tap control circuit 91 except that inputsignal evaluation circuit 170 is replaced with input signal evaluationcircuit 174, detailed operations described below will be centered on thedifference.

[0168] Input signal evaluation circuit 174 is supplied with input signalsamples at outputs of delay elements 20 _(i) through input terminals 905₁-905 _(L). The actual value of i is defined by path switch 7. Inputsignal evaluation circuit 174 uses these input signal samples toevaluate input signal power. When the evaluated input signal power issmaller than a first predefined threshold value, input signal evaluationcircuit 174 delivers a coefficient update stop signal. Also, when theevaluated input signal power is smaller than a second predefinedthreshold value, input signal evaluation circuit 174 delivers a tapposition update stop signal.

[0169] Input signal evaluation circuit 174 also transfers the evaluatedinput signal power to output terminal 909. This value is supplied tocontrol circuit 71 and used for distributing the number of coefficientupdates. Since the operations for stopping the coefficient update andtap position update using the coefficient update stop signal and tapposition update stop signal are completely identical to those of inputsignal evaluation circuit 170, description thereon is omitted.

[0170] The configuration of input signal evaluation circuit 170illustrated in FIG. 13 can be used as it is for the configuration ofinput signal evaluation circuit 174. It should be noted that N squarecircuits 1701 ₀-1701 _(N−1) are disposed in FIG. 13 because there are Ntypes of inputs, whereas input signal evaluation circuit 174 needs onlyL square circuits 1701 ₀-1701 _(L−1).

[0171] Also, it goes without saying that the configurations illustratedin FIGS. 14, 15, 16 can also be used for the configuration of inputsignal evaluation circuit 174 when the number of square circuits andabsolute value circuit is increased or decreased in a similar manner.Further, only some of inputs supplied to and processed by input signalevaluation circuit 174 may be added in adder circuit 1704, as is thecase with input signal evaluation circuit 170.

[0172] A tenth embodiment of the present invention is provided bysubstituting tap control circuit 93 for tap control circuit 91 describedin the block diagram illustrating the fifth embodiment of the presentinvention shown in FIG. 11. FIG. 19 is a block diagram illustrating theconfiguration of tap control circuit 93. Since FIG. 19 is identical toFIG. 18 except that input signal evaluation circuit 174 is replaced withinput signal evaluation circuit 175, the detailed operations describedbelow will be centered on the difference.

[0173] Input signal evaluation circuit 174 in FIG. 18 receives inputsignal samples supplied to active taps from path switch 7 to evaluatethe input signal power. Based on the result of the evaluation, inputsignal evaluation circuit 174 delivers a coefficient update stop signaland a tap position update stop signal. On the other hand, input signalevaluation circuit 175 in FIG. 19 receives input signal samples at aninput of delay element 20 ₁ and outputs of 20 ₁-20 _(N−1) to evaluateinput signal power, and outputs a coefficient update stop signal and atap position update stop signal based on the result of the evaluation,in a manner similar to input signal evaluation circuit 174. In thisevent, input signal evaluation circuit 175 selectively uses only inputsignal samples supplied from delay elements corresponding to activetaps.

[0174] For this reason, input signal evaluation circuit 175 is suppliedwith a tap position control signal from memory circuit 114. Statedanother way, input signal evaluation circuit 174 and input signalevaluation circuit 175 are different in configuration but equal inoperation, and signals delivered therefrom are also compatible. Sincecomponents other than input signal evaluation circuit 175 in tap controlcircuit 93 are completely identical to components except for inputsignal evaluation circuit 174 in tap control circuit 92, without anydifference in operation, detailed description thereon is omitted.

[0175] An eleventh embodiment of the present invention is provided bysubstituting tap control circuit 94 for tap control circuit 92 describedin the block diagram illustrating the ninth embodiment of the presentinvention shown in FIG. 18. Since a difference between the eleventhembodiment and ninth embodiment of the present invention lies only intap control circuit 94, tap control circuit 94 will be described belowwith reference to FIG. 20.

[0176]FIG. 20 is block diagram illustrating the configuration of tapcontrol circuit 94. Since FIG. 20 is identical to FIG. 18 which is theblock diagram of tap control circuit 92 except that coefficient valueevaluation circuit 130 is replaced with coefficient value evaluationcircuit 131, detailed operation described below will be centered on thedifference.

[0177] Coefficient value evaluation circuit 130 in FIG. 18 calculates asum total of absolute coefficient values for each tap group as the“coefficient sum,” whereas coefficient value evaluation circuit 131 inFIG. 20 calculates a sum total of squared coefficient values for eachtap group. The calculated sum total of the squared coefficient values istransferred to tap group selection information update circuit 140. Also,the ratio R_(j) transferred to step size generator circuit 160 iscalculated in accordance with R_(j)=C_(j,max)/C_(max), where C_(j,max)is the sum total of the squared coefficient values (1≦j≦M) without usingsum totals of absolute coefficient values in respective tap groups.C_(max) is a maximum value of the sum totals of squared coefficientvalues in the respective tap groups. Since components other thancoefficient value evaluation circuit 131 in tap control circuit 94 arecompletely identical to components other than coefficient valueevaluation circuit 130 in tap control circuit 92, without any differencein operation, detailed description will be omitted. Basically, thedescription on tap control circuit 92 can be applied to the descriptionon tap control circuit 94 by replacing the absolute coefficient valueswith the squared coefficient values.

[0178] A twelfth embodiment of the present invention is provided bysubstituting tap control circuit 95 illustrated in FIG. 21 for tapcontrol circuit 91 described in the block diagram illustrating the fifthembodiment of the present invention shown in FIG. 11. A differencebetween the twelfth embodiment and fifth embodiment of the presentinvention lies only in tap control circuit 95. Also, the relationshipbetween tap control circuit 91 and tap control circuit 95 is equal tothe relationship between tap control circuit 92 and tap control circuit94, as previously described with reference to FIG. 19, so that detaileddescription thereon will be omitted.

[0179] A thirteenth embodiment of the present invention is provided bysubstituting tap control circuit 96 for tap control circuit 92 describedin the block diagram illustrating the ninth embodiment of the presentinvention shown in FIG. 18. Since a difference between the thirteenthembodiment and ninth embodiment of the present invention lies only intap control circuit 96, tap control circuit 96 will be described belowwith reference to FIG. 22.

[0180]FIG. 22 is a block diagram illustrating the configuration of tapcontrol circuit 96. Since FIG. 22 is identical to FIG. 18 which is theblock diagram of tap control circuit 92 except for coefficient valueevaluation circuit 130 and maximum coefficient detector circuit 132,detailed operation described below will be centered on the difference.Coefficient value evaluation circuit 130 calculates a sum total ofabsolute coefficient values for each tap group as the “coefficient sum,”whereas maximum coefficient detector circuit 132 detects a coefficientvalue having a maximum absolute value for each tap group. The detectedmaximum absolute coefficient value is transferred to tap group selectioninformation update circuit 140 as a “maximum coefficient value.” A timeduring which each tap group is continuously selected is calculated basedon the “maximum coefficient value” instead of the “coefficient sum.”Also, these M maximum values are rearranged according to the magnitude,and corresponding tap group indexes are transferred to tap groupselection information update circuit 140 as the “order.”

[0181] Maximum coefficient detector circuit 132 calculates the ratio ofa maximum value C_(max) of maximum coefficient values in respective tapgroups to a maximum coefficient value in each tap group. For example,assuming that the maximum coefficient value in each tap group isc_(j,max) (1≦j≦M) when the number of tap groups is M, the ratioR_(j)=c_(j,max)/C_(max) is calculated therefor and transferred to stepsize generator circuit 160. A similar result can also be provided when asum total of the maximum coefficient values in each tap group is definedas C_(max).

[0182] Since components other than maximum coefficient detector circuit132 in tap control circuit 96 are completely identical to componentsother than coefficient value evaluation circuit 130 in tap controlcircuit 92, without any difference in operation, detailed descriptionthereon is omitted. Basically, the description on tap control circuit 92can be applied to the description on tap control circuit 96 by replacingthe sum total of absolute coefficient values with the maximum absolutecoefficient value.

[0183] A fourteenth embodiment of the present invention is provided bysubstituting tap control circuit 97 illustrated in FIG. 23 for tapcontrol circuit 91 described in the block diagram illustrating the fifthembodiment of the present invention shown in FIG. 11. A differencebetween the fourteenth embodiment and fifth embodiment of the presentinvention lies only in tap control circuit 97. Also, the relationshipbetween tap control circuit 91 and tap control circuit 97 is equal tothe relationship between tap control circuit 92 and tap control circuit96, as previously described with reference to FIG. 22, so that detaileddescription thereon will be omitted.

[0184] A fifteenth embodiment of the present invention is provided bysubstituting tap control circuit 98 for tap control circuit 92 describedin the block diagram illustrating the ninth embodiment of the presentinvention shown in FIG. 18. Since a difference between the fifteenthembodiment and ninth embodiment of the present invention lies only intap control circuit 98, tap control circuit 98 will be described belowwith reference to FIG. 24.

[0185]FIG. 24 is a block diagram illustrating the configuration of tapcontrol circuit 98. Since FIG. 24 is identical to FIG. 18 which is theblock diagram of tap control circuit 92 except for coefficient valueevaluation circuit 130 and active tap number evaluation circuit 133,detailed operations described below will be centered on the difference.

[0186] Coefficient value evaluation circuit 130 in FIG. 18 calculates asum total of absolute coefficient values for each tap group as the“coefficient sum,” whereas active tap number evaluation circuit 133detects the number of active taps for each tap group. The detectednumber of active taps is transferred to tap group selection informationupdate circuit 140 as a “number”. Tap group selection information updatecircuit 140 calculates a time for which each tap group is continuouslyselected based on the “number” instead of the “coefficient sum.”

[0187] Active tap number evaluation circuit 133 also calculates theratio of a maximum value C_(max) of the numbers of active taps in therespective tap groups to the number of active taps in each tap group.For example, assuming that the number of active taps in each tap groupis c_(j,max) (1≦j≦M) when the number of tap groups is M, the ratioR_(j)=c_(j,max)/C_(max) is calculated therefor and transferred to stepsize generator circuit 160. A similar result can also be provided whenthe total number of the active taps in each tap group is defined asC_(max).

[0188] Since components other than active tap number evaluation circuit133 in tap control circuit 98 are completely identical to componentsother than coefficient value evaluation circuit 130 in tap controlcircuit 92, without any difference in operation, detailed descriptionthereon is omitted. Basically, the description on tap control circuit 92can be applied to the description on tap control circuit 98 by replacingthe absolute coefficient values with the number of active taps.

[0189] The sixteenth embodiment of the present invention is provided bysubstituting tap control circuit 99 illustrated in FIG. 25 for tapcontrol circuit 91 described in the block diagram illustrating the fifthembodiment of the present invention shown in FIG. 11. A differencebetween the fifteenth embodiment and fifth embodiment of the presentinvention lies only in tap control circuit 99. Also, the relationshipbetween tap control circuit 91 and tap control circuit 99 is equal tothe relationship between tap control circuit 92 and tap control circuit98, as previously described with reference to FIG. 24, so that detaileddescription thereon will be omitted.

[0190] In the description on the fifth to sixteenth embodiments of thepresent invention, coefficient value evaluation circuit 131, maximumcoefficient detector circuit 132, and active tap number evaluationcircuit 133 have been described as coefficient value evaluation circuit130 and equivalent circuits thereof. The basic operation of thesecircuits involves receiving active taps and their coefficient valuesfrom memory circuit 114 and input terminals 903 ₁-903 _(L), andtransferring to tap group selection information update circuit 140 thevalues of first evaluation indexes as well as the indexes on respectivetap groups in the decreasing order. The basic operation of thesecircuits also includes representing the degree of non-uniformity for thevalue of a second evaluation index on each tap group as the ratio of atotal sum of the second evaluation indexes to the second evaluationindex of each tap group or the ratio of a maximum value of the secondevaluation indexes with the second evaluation index of each tap group,and transferring the ratio to step size generator circuit 160.

[0191] The foregoing description has shown a sum total of absolutecoefficient values, a sum total of squared coefficient values, a maximumvalue of absolute coefficient values, and the number of active taps asexamples of the first evaluation index and second evaluation index.Also, the description has been made on the assumption that these indexesare identical. However, it is also possible to use an index other thanthose shown as examples, and to employ a first evaluation indexdifferent from a second evaluation index. Next described is an exemplarycombination of such different first evaluation index and secondevaluation index.

[0192] A seventeenth embodiment of the present invention is provided bysubstituting tap control circuit 100 for tap control circuit 92described in the block diagram illustrating the ninth embodiment of thepresent invention shown in FIG. 18. Since a difference between theseventeenth embodiment and eighth embodiment of the present inventionlies only in tap control circuit 100, tap control circuit 100 will bedescribed below with reference to FIG. 26.

[0193]FIG. 26 is a block diagram illustrating the configuration of tapcontrol circuit 100. Since FIG. 26 is identical to FIG. 18 which is theblock diagram of tap control circuit 92 except for coefficient valueevaluation circuit 130 and coefficient value evaluation circuit 134,detailed operation described below will be centered on the difference.Coefficient value evaluation circuit 134 receives tap coefficient valuesdelivered from respective coefficient generator circuits, and active tapindexes delivered from memory circuit 114, and transfers the“coefficient sum” and “order,” which are calculated in a completelysimilar procedure to coefficient value evaluation circuit 130, to tapgroup selection information update circuit 140. Maximum coefficientdetector circuit 134 in turn calculates the ratio of a maximum valueC_(max) of maximum absolute coefficient values in respective tap groupsto the maximum absolute coefficient value in each group. For example,assuming that the maximum absolute value in each tap group is c_(j,max)(1≦j≦M) when the number of tap groups is M, the ratioR_(j)=c_(j,max)/C_(max) is calculated therefor and transferred to stepsize generator circuit 160. A similar result can also be provided when asum total of the maximum absolute coefficient values in each tap groupis defined as C_(max).

[0194] The description on the fifth to seventeenth embodiments of thepresent invention has been made in connection with an example in whichstep size generator circuit 160 generates a different step size for eachtap group. However, an eighteenth embodiment can be provided bydesigning step size generator circuit 160 to generate an equal step sizeto each tap group.

[0195]FIG. 27 is a block diagram illustrating the eighteenth embodimentof the present invention. The eighteenth embodiment differs from theninth embodiment in that tap control circuit 92 in FIG. 18 is replacedwith tap control circuit 101 in FIG. 27.

[0196] Tap control circuit 92 in FIG. 18 supplies different step sizesto coefficient generator circuits 30 ₁-30 _(L) through output terminals901 ₁-901 _(L), whereas tap control circuit 101 in FIG. 28 supplies acommon step size to coefficient generator circuits 30 ₁-30 _(L) throughoutput terminal 901. For this reason, tap control circuit 101 has onlyoutput terminal 901 instead of a plurality of output terminals 901 ₁-901_(L).

[0197]FIG. 28 is a block diagram illustrating the configuration of tapcontrol circuit 101. Since FIG. 28 is identical to FIG. 18 except forstep size generator circuit 160 and step size generator circuit 161, theoperation described below will be centered on the difference.

[0198] Unlike step size generator circuit 160, step size generatorcircuit 161 in FIG. 28 does not receive R_(j) supplied from coefficientvalue evaluation circuit 130. Step size generator circuit 161 neitherreceives information on active taps supplied from memory circuit 114.Step size generator circuit 161 sets a step size supplied to outputterminal 901 to zero only when it is supplied with a coefficient updatestop signal from input signal evaluation circuit 174. Otherwise, stepsize generator circuit 161 supplies output terminal 901 with apredefined value as a common step size for coefficient generatorcircuits 30 ₁-30 _(L).

[0199]FIG. 29 is a block diagram illustrating the configuration of stepsize generator circuit 161. Step size generator circuit 161 comprisesmemory circuit 1610 and switch 1611. Memory circuit 1610 stores zero andμ as the normal step size, and supplies them to two input terminals ofswitch 1611. Switch 1611 is controlled by the coefficient update stopsignal supplied from input signal evaluation circuit 174. Switch 1611normally selects μ supplied from memory circuit 1610 and delivers thesame as the step size, but it operates to select and deliver zero whenit is supplied with the coefficient update stop signal from input signalevaluation circuit 174.

[0200] As is apparent from the foregoing description, in tap controlcircuit 101, input signal evaluation circuit 174 for generating thecoefficient update stop signal can be replaced with input signalevaluation circuit 170, input signal evaluation circuit 171, inputsignal evaluation circuit 172, or input signal evaluation circuit 173.Also, step size generator circuit 161 can be used in place of step sizegenerator circuit 160 in any of tap control circuit 91, tap controlcircuit 92, tap control circuit 93, tap control circuit 94, tap controlcircuit 95, tap control circuit 96, tap control circuit 97, tap controlcircuit 98, tap control circuit 99, and tap control circuit 100.

[0201] While the foregoing embodiments of the present invention havebeen described in connection with the update of tap coefficients usingthe LMS algorithm as an example, a variety of other algorithms can beapplied. For example, the normalized LMS (NLMS) algorithm described inReference 2 may be used instead of the LMS algorithm in the fourthembodiment of the present invention to provide the eighteenth embodimentof the present invention.

[0202] A nineteenth embodiment of the present invention is provided bysubstituting tap control circuit 102 for tap control circuit 92described in the block diagram illustrating the ninth embodiment of thepresent invention shown in FIG. 18. Since a difference between thenineteenth embodiment and ninth embodiment of the present invention liesonly in tap control circuit 102, tap control circuit 102 will bedescribed below with reference to FIG. 30.

[0203]FIG. 30 is a block diagram illustrating the configuration of tapcontrol circuit 102. Since FIG. 30 is identical to FIG. 18 except forstep size generator circuit 162 and input signal evaluation circuit 176,detailed operations described below will be centered on the difference.

[0204] The largest difference between tap control circuit 92 and tapcontrol circuit 102 lies in that step size generator circuit 162 issupplied with active tap input signal power from input signal evaluationcircuit 176. A filter coefficient update, when using the NLMS algorithm,is given by: $\begin{matrix}{{c_{i}\left( {k + 1} \right)} = {{c_{i}(k)} + {\mu_{i}\frac{{e(k)}{x\left( {k - {a(i)}} \right)}}{\sum\limits_{l = 1}^{L}\quad {x^{2}\left( {k - {a(i)}} \right)}}}}} & (19)\end{matrix}$

[0205] where a(i) is a set which is composed of active tap indexes, asdescribed in line with Equation (17), and the number of elements is L.From a comparison of Equation (19) with Equation (17) representative ofthe LMS algorithm, it can be seen that a difference lies innormalization of the second term on the right hand side:$\sum\limits_{i = 1}^{L}{x^{2}\left( {k - {a(i)}} \right)}$

[0206] This active tap input signal power is calculated in input signalevaluation circuit 176 and supplied to step size generator circuit 162.Since components other than step size generator circuit 162 and inputsignal evaluation circuit 176 in tap control circuit 102 are completelyidentical to components other than step size generator circuit 160 andinput signal evaluation circuit 174 in tap control circuit 92, withoutany difference in operation, detailed description thereon is omitted.

[0207] In the configuration of the ninth embodiment of the presentinvention, the LMS algorithm can be replaced with the NLMS algorithmwithout replacing tap control circuit 92. This will be described as atwentieth embodiment of the present invention.

[0208]FIG. 31 is a block diagram illustrating the twentieth embodimentof the present invention. The twentieth embodiment differs from theninth embodiment in that coefficient generator circuits 30 ₁-30 _(L) arereplaced with coefficient generator circuits 300 ₁-300 _(L) and powerevaluation circuit 11 is additionally provided. Power evaluation circuit11 is supplied with input signal samples fed to active taps, similar toinput terminals 905 ₁-905 _(L). Power evaluation circuit 11 calculates:$\sum\limits_{i = 1}^{L}{x^{2}\left( {k - {a(i)}} \right)}$

[0209] and supplies its inverse to coefficient generator circuits 300₁-300 _(L) as a normalization coefficient.

[0210]FIG. 32 is a block diagram illustrating the configuration ofcoefficient generator circuit 300 _(i) (i=1, 2, . . . , L). A differencebetween coefficient generator circuit 300 _(i) and coefficient generatorcircuit 30 _(i) (i=1, 2, . . . , L) illustrated in FIG. 10 lies in thatan output signal of multiplier 31 is multiplied by the normalizationcoefficient in multiplier 35 before it is supplied to multiplier 32.With this difference, the amount of modification to coefficients, whichis the output of multiplier 32, is expressed by:$\frac{1}{\sum\limits_{i = 1}^{L}{x^{2}\left( {k - {a(i)}} \right)}}$

[0211] as compared with the output of multiplier 32 in FIG. 10, thusimplementing the coefficient update equation shown in Equation (19).Since the remaining configuration and operation associated withcoefficient generator circuit 300 _(i) (i=1, 2, . . . , L) are identicalto those of coefficient generator circuit 30 _(i) (i=1, 2, . . . , L),description thereon is omitted.

[0212] In the fifth embodiment illustrated in FIG. 9, the NLMS algorithmmay be used as well instead of the LMS algorithm to provide a twentyfirst embodiment of the present invention.

[0213]FIG. 33 is a block diagram illustrating the twenty firstembodiment of the present invention. The twenty first embodiment differsfrom the fifth embodiment in that coefficient generator circuits 30 ₁-30_(L) are replaced with coefficient generator circuits 300 ₁-300 _(L) andpower evaluation circuit 11 is additionally provided. Since thedifference between the fifth embodiment and twenty first embodiment isequal to the difference between the ninth embodiment and the twentiethembodiment, which has been already described, description thereon isomitted.

[0214] While the coefficient update algorithm is changed herein for thefourth and eighth embodiments of the present invention, it should beclear that a similar change can be made to the fifth to seventh andninth to eighteenth embodiments of the present invention. Also, theeighteenth, nineteenth and twentieth embodiments of the presentinvention can be configured to generate an equal step size for each tapgroup, as is the case with the seventeenth embodiment of the presentinvention.

[0215] In satellite links, there is known a phenomenon called phase rollwhich is instantaneous inversion of the polarity of an echo pathidentified by an adaptive filter. When the phase roll is encountered, itis necessary to follow fluctuations in impulse response of the echo paththrough a coefficient update, wherein a larger number of coefficientupdates are required even if coefficient adaptation is close toconvergence. To address this problem, the phase roll is detected, andtap position information transferred to control circuit 71 is reset tovalues immediately after the coefficient update was started, therebymaking it possible to allocate a larger number of coefficient updates.

[0216]FIG. 34 illustrates tap control circuit 103 which can be used inplace of tap control circuit 91 in FIG. 10 for such a purpose.

[0217] Tap control circuit 103 in FIG. 34 differs from tap controlcircuit 91 in FIG. 11 in that tap control circuit 103 comprises maximumcoefficient detector circuit 117 and evaluation circuit 115. Maximumcoefficient detector circuit 117 is supplied with coefficient valuesthrough input terminals 903 ₁-903 _(L). Maximum coefficient detectorcircuit 117 detects a maximum of these coefficient values which istransferred to evaluation circuit 115. Evaluation circuit 115 evaluateschanges in the maximum coefficient value supplied thereto, and suppliesa control signal to maximum value detector circuit 180 when the changeis larger than a predefined value. Upon receipt of the control signalfrom evaluation circuit 115, maximum value detector circuit 180 operatesto reset a maximum coefficient sum, which is its output, to a predefinedvalue, to ensure a larger number of updates in the distribution of thenumber of coefficient updates in the control circuit.

[0218] Maximum coefficient detector circuit 117 can employ, for example,a procedure shown below for detecting the maximum coefficient.

[0219] 1. Define an N₀-th coefficient as a maximum value.

[0220] 2. Compare an (N₀+1)th coefficient with the maximum value todefine the larger one as a maximum value.

[0221] 3. Subsequently, perform the comparison and replacement insequence from the (N₀+2)th coefficient.

[0222] N₀ is generally set to 1. When no restrictions are imposed on theamount of operations, the foregoing manipulations can be performed in asingle sampling period to immediately find the maximum coefficientvalue. Alternatively, the amount of operations can be reduced byperforming the foregoing manipulations one by one in each samplingperiod. While these manipulations are performed, a maximum value at thattime is regarded as the maximum coefficient value which is transferredto evaluation circuit 115.

[0223] Changes in the maximum coefficient value can be evaluated inevaluation circuit 115, for example, in accordance with Equations (3)and (16). In other words, evaluation circuit 115 evaluates theproportion of a change between the preceding value and the current valueto the current value. While the foregoing description has been made onthe configuration of tap control circuit 103 which comprises the phaseroll detecting mechanism added to tap control circuit 91, it is apparentthat a similar modification can be made to tap control circuits 92-102.

[0224] A similar system change detecting mechanism can further be addedto the first to fourth embodiments. Other than the previously describedmethod of monitoring a maximum coefficient value, any method can beapplied for detecting changes in a system, as represented by a methoddescribed in JOURNAL OF THE INSTITUTE OF ELECTRONICS, INFORMATION ANDCOMMUNICATION ENGINEERS, pp. 314-322, March 1995 (Reference 13). Whilethe fifth to twenty first embodiments so far described assume that thenumber of coefficients subjected to relocation in a single tap controlis one, two or more coefficients can be relocated.

[0225] In all the embodiments so far described, while the LMS algorithmand NLMS algorithm have been assumed as an algorithm for the adaptivefilter, a sequential regression algorithm (SRA) described in Reference1, the RLS algorithm described in Reference 2, and the like can be usedin a similar manner. For examples of specific configurations therefor,description is omitted. Further, while the embodiments of the presentinvention have been described in detail in connection with an echocanceler taken as an example, the present invention can be applied aswell to a noise canceler, a howling canceler, an adaptive equalizer, andthe like in similar principles.

[0226] The present invention evaluates intensities of signals fed tomultiplexed lines and the convergence degree of an adaptive filter oneach line to distribute a predefined number of coefficient updates toeach line in accordance with the signal intensities and convergencedegrees, so that even if the number of multiplexed lines is increased,the amount of required operations will not increase in proportion to thenumber of lines.

1. An echo canceling method for multiplexed lines, wherein an adaptivefilter is installed on each line to cancel echoes on the multiplexedlines, said method, comprising the steps of: evaluating a convergencedegree and an input signal intensity of each adaptive filter providedfor said each line; and distributing a total number of coefficientupdates per unit time given by a predefined number for all the lines inaccordance with said convergence degree and input signal intensity. 2.The echo canceling method for multiplexed lines according to claim 1,comprising the steps of: averaging at least one of said convergencedegrees and input signal intensities of said adaptive filters; anddistributing said total number of coefficient updates using saidaveraged value.
 3. The echo canceling method for multiplexed linesaccording to claim 2, wherein said distribution of said total number ofcoefficient updates includes first allocating a predefined number to allthe lines, and distributing a remainder in accordance with saidconvergence degrees and input signal intensities.
 4. The echo cancelingmethod for multiplexed lines according to claim 1, wherein saidconvergence degree of said adaptive filter is evaluated based oninformation on at least one of coefficient values supplied from saideach adaptive filter.
 5. The echo canceling method for multiplexed linesaccording to claim 2, wherein said convergence degree of said adaptivefilter is evaluated based on information on at least one of coefficientvalues supplied from said each adaptive filter.
 6. The echo cancelingmethod for multiplexed lines according to claim 3, wherein saidconvergence degree of said adaptive filter is evaluated based oninformation on at least one of coefficient values supplied from saideach adaptive filter.
 7. The echo canceling method for multiplexed linesaccording to claim 2, wherein said adaptive filter adaptively controlspositions of taps such that tap coefficients are located around aposition of dispersive regions obtained by eliminating fixed delays froman impulse response of an echo path.
 8. The echo canceling method formultiplexed lines according to claim 3, wherein said adaptive filteradaptively controls positions of taps such that tap coefficients arelocated around a position of dispersive regions obtained by eliminatingfixed delays from an impulse response of an echo path.
 9. The echocanceling method for multiplexed lines according to claim 4, whereinsaid adaptive filter adaptively controls positions of taps such that tapcoefficients are located around a position of dispersive regionsobtained by eliminating fixed delays from an impulse response of an echopath.
 10. The echo canceling method for multiplexed lines according toclaim 5, wherein said adaptive filter adaptively controls positions oftaps such that tap coefficients are located around a position ofdispersive regions obtained by eliminating fixed delays from an impulseresponse of an echo path.
 11. The echo canceling method for multiplexedlines according to claim 6, wherein said adaptive filter adaptivelycontrols positions of taps such that tap coefficients are located arounda position of dispersive regions obtained by eliminating fixed delaysfrom an impulse response of an echo path.
 12. An echo cancelingapparatus for multiplexed lines comprising: a plurality of adaptivefilters provided for a plurality of lines, respectively; and a controlcircuit for receiving information on convergence degrees and inputsignal intensities from said plurality of adaptive filters to generate acoefficient update control signal for controlling a number ofcoefficient updates in each said adaptive filter by distributing a totalnumber of coefficient updates per unit time given by a predefined numberfor all the lines in accordance with said convergence degrees and inputsignal intensities.
 13. The echo canceling apparatus for multiplexedlines according to claim 12, wherein said control circuit comprises anaveraging circuit for averaging at least one of the convergence degreesand the input signal intensities of said adaptive filters.
 14. The echocanceling apparatus for multiplexed lines according to claim 13, whereinsaid control circuit distributes the total number of coefficient updatesby first distributing a predefined number to all the lines, anddistributing a remainder in accordance with said convergence degrees andinput signal intensities.
 15. The echo canceling apparatus formultiplexed lines according to claim 12, wherein said control circuitreceives information on at least one coefficient value as theconvergence degree of said adaptive filter, and distributes the totalnumber of coefficient updates in accordance with the information on thecoefficient value and the input signal intensities.
 16. The echocanceling apparatus for multiplexed lines according to claim 13, whereinsaid control circuit receives information on at least one coefficientvalue as the convergence degree of said adaptive filter, and distributesthe total number of coefficient updates in accordance with theinformation on the coefficient value and the input signal intensities.17. The echo canceling apparatus for multiplexed lines according toclaim 14, wherein said control circuit receives information on at leastone coefficient value as the convergence degree of said adaptive filter,and distributes the total number of coefficient updates in accordancewith the information on the coefficient value and the input signalintensities.
 18. The echo canceling apparatus for multiplexed linesaccording to claim 13, wherein said plurality of adaptive filters eachcomprise a tap control circuit for adaptively controlling positions oftaps such that tap coefficients are located around a position ofdispersive regions obtained by eliminating fixed delays from an impulseresponse of an echo path.
 19. The echo canceling apparatus formultiplexed lines according to claim 14, wherein said plurality ofadaptive filters each comprise a tap control circuit for adaptivelycontrolling positions of taps such that tap coefficients are locatedaround a position of dispersive regions obtained by eliminating fixeddelays from an impulse response of an echo path.
 20. The echo cancelingapparatus for multiplexed lines according to claim 15, wherein saidplurality of adaptive filters each comprise a tap control circuit foradaptively controlling positions of taps such that tap coefficients arelocated around a position of dispersive regions obtained by eliminatingfixed delays from an impulse response of an echo path.
 21. The echocanceling apparatus for multiplexed lines according to claim 16, whereinsaid plurality of adaptive filters each comprise a tap control circuitfor adaptively controlling positions of taps such that tap coefficientsare located around a position of dispersive regions obtained byeliminating fixed delays from an impulse response of an echo path. 22.The echo canceling apparatus for multiplexed lines according to claim17, wherein said plurality of adaptive filters each comprise a tapcontrol circuit for adaptively controlling positions of taps such thattap coefficients are located around a position of dispersive regionsobtained by eliminating fixed delays from an impulse response of an echopath.